Local interconnect structures and methods for making the same

ABSTRACT

The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silicon source layer preferably comprising silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (i.e., does not comprise polysilicon). The silicon source layer is preferably deposited over an active area in the substrate and at least a portion of the topographical structure. A silicide forming material, e.g., a refractory metal, is deposited directly on selected regions of the silicon source layer and over the topographical structure. A silicide layer is made from the silicide forming material and the silicon source layer preferably by annealing the structure. The silicide layer defines a portion of the local interconnect structure, unreacted silicide forming material is removed and an interlevel dielectric is formed over the silicide layer. The interlevel dielectric includes a recess defined substantially over the active area and an electrically conductive material is deposited in the recess. The present invention also provides local interconnect structures.

FIELD OF THE INVENTION

[0001] The present invention relates to local interconnect structures inan integrated circuit, and methods for making the same.

BACKGROUND OF THE INVENTION

[0002] A continuing trend in semiconductor technology is to buildintegrated circuits with more and faster semiconductor devices. Thedrive toward this ultra large-scale integration has resulted in acontinued shrinking of device and circuit features. To take advantage ofan increasing number of devices and to form the devices into one or morecircuits, the various devices must be interconnected.

[0003] Ultra-large scale integrated circuit technology includes theformation of isolated semiconductor devices formed within the surface ofsilicon wafers and interconnecting these devices with wiring layersabove the surface. The interconnection system typically consists of twoor more levels of interconnection metallurgy, separated by insulationlayers. The first level of interconnection is used to define smallfundamental circuits, e.g., a basic CMOS inverter requiring that thegates on NMOS and PMOS devices are connected together. Memory cells suchas 6T SRAM, in particular, require several such local interconnections.

[0004] To accomplish interconnection on such a small scale, a localinterconnect is typically used within an integrated circuit to providean electrical connection between two or more conducting orsemiconducting regions (e.g., active regions of one or more devices).More specifically, local interconnects are routing-restrictedinterconnect levels used for the short metallization runs, such as thosethat locally interconnect gates and drains in NMOS and CMOS circuits andthose that connect a given metallization layer to a particular structurewithin the integrated circuit.

[0005] Local interconnects are typically formed of low resistancematerial, such as a conductor or a doped semiconductor that is formed toelectrically couple selected regions. A commonly used technique forforming local interconnects is the Damascene process. In this process afirst metal is inlaid into a dielectric layer. This involves firstdepositing the dielectric layer and then polishing via chemicalmechanical polishing (CMP) to make the layer planar. The structure isthen patterned and etched to form recessed trenches in the dielectriclayer where conductive metal lines are to be deposited. Contact to theunderlying devices is made where the trenches pass over the activedevice regions; elsewhere the dielectric layer insulates the metal fromthe substrate. Generally, a sandwich structure of titanium (Ti),titanium nitride (TiN), and tungsten is next deposited in the trench andonto the dielectric surface. A second CMP is then used to remove theconductive materials from the dielectric surface, leaving metal in thetrench. The CMP step is followed by a next level of interleveldielectric (ILD) deposition, contact patterning and etching, and afilling with a conductive metal. Due to time and associated costs, it isundesirable to require two CMP processes to form a local interconnectstructure.

[0006] Other methods for forming local interconnects have been used ineffort to avoid the multiple CMP processing steps required by theDamascene technique. Such methods use a polycrystalline silicon(polysilicon) layer as a silicon source layer. Typically, titanium (ortitanium nitride, Ti_(x)N_(y), wherein y is less than about 0.12) isdeposited over a device. Polysilicon is then deposited as a uniformlayer over the titanium. An interconnect pattern is formed thereon andportions of the polysilicon layer are removed. The device is thenannealed so that the titanium in contact with the polysilicon forms atitanium silicide. The remaining titanium (that did not react with thepolysilicon) is removed. Theoretically, this process allows formation ofself-aligned local interconnects. In practice, however, titanium thatdoes not overly the polysilicon source layer nonetheless typicallyleaches silicon (i.e., reacts with free silicon) from those portions ofthe polysilicon source layer that are adjacent the titanium resulting inthe formation of stringers. Stringers cause electrical shorting betweendevices.

SUMMARY OF THE INVENTION

[0007] To overcome the deficiencies in the prior art, the presentinvention provides local interconnect structures that are free ofstringers. The present invention also provides methods for making suchlocal interconnect structures wherein the methods do not require two ormore CMP processing steps. Because local interconnect structures formelectrical connections of relatively short distances (typically about0.5 μm to about 10 μm), the material forming the local interconnectsneed not possess a low resistance value (as compared to materialsforming electrical interconnections of greater distances (i.e.,typically distances greater than 10 μm)). Accordingly, materials otherthan polycrystalline silicon are used in the present invention to form asilicon source layer for fabrication of local interconnect structures.

[0008] The present invention provides methods for forming a localinterconnect structures for integrated circuits. In a representativemethod, a substrate having a surface and including at least onetopographical structure thereon (such that a region of the surface ofthe substrate is exposed) is provided. An active area is preferablyformed in the substrate prior to formation of the topographicalstructure. A thin silicon source layer is then deposited over at least aportion of the active area. The silicon source layer preferablycomprises silicon rich silicon nitride, silicon oxynitride or othersilicon source having sufficient free silicon to form a silicide but notso much free silicon as to result in formation of stringers (as occurswith the use of polysilicon). A silicide forming material, such as arefractory metal, is deposited directly upon selected regions of thesilicon source layer and over the topographical structure. The structureis then preferably annealed to form a silicide layer from the refractorymetal and silicon source layer. The silicide layer creates a portion ofthe local interconnect structure. Remaining non-reacted silicide formingmaterial (e.g., regions of the silicon source layer not in direct,intimate contact with the silicide forming material) is removed and aninterlevel dielectric is deposited over the suicide layer. Theinterlevel dielectric includes at least one recess defined substantiallyover the active area. An electrically conductive material is depositedin the recess to complete the local interconnect structure.

[0009] According to another representative embodiment a method offorming a local interconnect structure for an integrated circuit isprovided wherein a silicide forming material, e.g., a refractory metal,is deposited prior to deposition of a silicon source layer. The siliconsource layer preferably comprises silicon rich silicon nitride, siliconoxynitride or other silicon source having sufficient free silicon toform a silicide but not so much free silicon as to result in formationof stringers. The silicon source layer is deposited over the refractorymetal and is patterned and etched to form a hard mask. The remainder ofthe method is essentially identical to the representative embodiment setforth above.

[0010] According to another aspect of the present invention, localinterconnect structures are provided. A representative embodiment of thelocal interconnect structure preferably includes a substrate having atleast one topographical structure, such as a gate stack. At least oneactive area is adjacent to the topographical structure. Silicon sourceoverlays a portion of the substrate and a portion of the topographicalstructure. A suicide layer covers at least a portion of the active areaand extends over a portion of the topographical structure therebyforming a portion of the local interconnect structure. An oxide layerpreferably overlays the silicon source but not the silicide layer. Apassivation layer covers the oxide layer and the silicide layer. Thepassivation layer includes at least one recess that extends through thepassivation layer and terminates substantially at the active area. Anelectrically conductive material substantially fills the recess to forman electrical contact with the silicide layer and the active area.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIGS. 1a-1 e show, in cross-section, a method of manufacture and aresulting local interconnect structure according to an embodiment of thepresent invention.

[0012]FIG. 2 is a process flow diagram of the method shown in FIGS. 1a-1e.

[0013]FIG. 3 is a cross-sectional view of an embodiment of the localinterconnect structure of the present invention.

[0014]FIGS. 4a-4 f show, in cross-section, another method of manufactureand a resulting local interconnect structure according to anotherembodiment of the present invention.

[0015]FIG. 5 is a process flow diagram of the method shown in FIGS. 4a-4f.

[0016]FIG. 6 is a cross-sectional view of another embodiment of thelocal interconnect structure of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0017] A first method of manufacture of an embodiment of a localinterconnect structure according to the present invention is describedwith reference to FIGS. 1a-1 e and FIG. 2.

[0018] Although the present invention is described primarily withreference to transistors as forming a part of the local interconnectstructure, it should be understood that the local interconnectstructures and manufacturing methods of the present invention applyequally well to any semiconductor device or integrated circuit requiringone or more local interconnects. For example, one application of thelocal interconnect structure of the present invention may be theformation of electrical interconnection between a transistor gate stackand a contact to an adjacent active area in a semiconductor substrate.

[0019]FIG. 1a illustrates a typical beginning structure for making alocal interconnection structure 10 (FIG. 3) of the present invention.The beginning structure may include a semiconductor or wafer substrate18 with at least one active region 14 defined in the substrate 18. Thesubstrate 18 may comprise silicon, gallium arsenide, glass, aninsulating material such as sapphire, or any other substrate materialupon which an integrated circuit wafer may be fabricated. Active regions14 are typically formed by doping specific portions of the wafersubstrate 18 by conventional methods, such as ion implantion ordiffusion. A field oxide or isolation region 20 is formed in thesubstrate 18.

[0020] The field oxide or isolation region 20 may be formed byconventional means known to persons skilled in the art, such as by localoxidation of a silicon substrate or isolation diffusion of the substrate18. Isolation region 20 forms p-n junctions that separate areas of thesubstrate 18. In other words, the isolation region 20, in part, servesthe function of a dielectric to electrically isolate regions of thesubstrate 18.

[0021] Materials are deposited on the substrate 18 and selectivelyremoved to form the desired topographical structure, such as atransistor gate stack 25. Although two complete gate stacks 25 areillustrated in FIGS. 1a-1 e, there can be any number of gate stacks 25or other various topographical structures formed upon the substrate 18.Gate stack 25 may comprise a gate oxide 22 having a transistor gate 24that typically comprises a polysilicon layer. Overlying the transistorgate 24 may be a metal silicide layer 28 (or some other conductorlayer). The refractory metal silicide 24 of the gate stack 25 typicallycomprises any refractory metal silicide including but not limited totitanium, cobalt, tungsten, tantalum, or molybdenum silicides.

[0022] Overlying the refractory metal silicide layer 28 is an insulatingmaterial cap 36, typically an oxide or nitride such as atetraethoxysilane (TEOS) oxide. Each gate stack 25 may include one ormore spacers 32. Spacers 32 are typically oriented perpendicular to thesubstrate 18 on either side of the gate stack 25. Spacers 32 may beformed by subjecting a layer of silicon nitride (not shown) depositedover the gate stack 25 to an anisotropic etch (a technique well known topersons skilled in the art). Alternatively, spacers 32 may be made ofundoped silicon dioxide.

[0023] As shown with the gate stack 25 positioned on the right side ofthe structure shown in FIG. 1a, a selected portion of the cap 36 may beremoved (e.g., by dry etch) to allow access to the transistor gate 24via the metal silicide layer 28. Alternatively, the cap 36 may beinitially deposited such that a portion of the metal silicide layer 28is exposed to allow access to the transistor gate 24.

[0024] Referring to FIG. 1b, a silicon source layer 42 is depositeduniformly over the structure. Silicon source layer 42 preferablycomprises silicon-rich silicon nitride or silicon oxynitride.Silicon-rich silicon nitride may be deposited by any method, but ispreferably deposited by LPCVD. Likewise, silicon oxynitride may bedeposited as a silicon source layer 42 by any method, but is preferablydeposited by PECVD using a reactant gas mixture of silane, nitrousoxide, ammonia, and nitrogen. The silicon source layer 42 preferably hasa thickness of from about 150 Å to about 400 Å and more preferably fromabout 150 Å to about 200 Å.

[0025] Stoichiometric silicon is Si₃N₄. As used herein, stoichiometricmeans that the composition is such that the ratio of elements forms aneutrally charged compound. Silicon-rich silicon nitride and siliconoxynitride are examples of nonstoichiometric materials. It is preferablethat the silicon source layer 42 have sufficient silicon concentrationto form the necessary silicide (i.e., so that the silicide issufficiently electrically conductive) but not too much silicon as tocause stringer formation during the silicide process. Accordingly, theapproximate stoichiometries for the silicon-rich silicon nitride orsilicon oxynitride are preferably equal to Si_(x)N_(y)O_(z) wherein x isabout 0.39 to about 0.65, y is about 0.02 to about 0.56, and z is about0.05 to about 0.33.

[0026] Continuing to refer to FIG. 1b, a thin film 44 is uniformlydeposited over the silicon source layer 42. Thin film 44 will beselectively removed to form a hard mask 46 as shown in FIG. 1c(discussed below). Thin film 44 may comprise any suitable insulatingmaterial that is not rich in silicon (i.e., without free silicon). Thinfilm 44 preferably comprises TEOS, Si₃N₄ or silicon oxynitride rich inoxygen and may be deposited by any suitable manner, such as by CVD. Thinfilm 44 preferably has a thickness of from about 200 Å to about 400 Å.

[0027] After deposition, the thin film 44 is patterned such thatportions of thin film 44 are exposed for removal to form hard mask 46.Patterned thin film 44 is etched using conventional etching techniques.Hard mask 46 assists in the selective removal of material during lateretching processes (discussed below) and defines the local interconnect.

[0028] Referring to FIG. 1c, after the hard mask 46 is formed by etchingthe patterned thin film 44, portions of the silicon source layer 42 areleft exposed. The hard mask 46 only covers portions of the siliconsource layer 42 where local interconnects will not be formed and exposesportions of silicon source layer 42 where local interconnects are to beformed.

[0029] Continuing to refer to FIG. 1c, a uniform layer of a refractorymetal 48 (or other electrically conductive, preferably silicide-formingmaterial) is deposited on the hard mask 46 and on the exposed portionsof the silicon source layer 42. Refractory metal 48 may be sputterdeposited or may be deposited by any other suitable method. Refractorymetal 48 preferably comprises titanium, titanium nitride (Ti_(x)N_(y),wherein y is from about 0.01 to about 0.15), cobalt, or colbalt nitride.Refractory metal 48 is preferably deposited at a thickness of from about300 Å to about 500 Å. The resulting structure is then annealed such thata metal silicide is formed.

[0030] The structure as shown in FIG. 1c is preferably annealed usingrapid thermal processing (RTP) in an N₂/NH₃ atmosphere at a temperatureof from about 700° C. to about 850° C., and more preferably from about700° C. to about 750° C. When the structure is annealed, refractorymetal 48 that is in intimate, direct contact with the exposed portionsof the silicon source layer 42.form metal silicide regions 52 (as shownin FIG. 1d). The portions of the silicon source layer 42 underlying thehard mask 46 do not react to form a silicide compound (but remain assilicon source layer material). Likewise the portions of refractorymetal 48 overlying the hard mask 46 do not react to form a silicidecompound. For example, if titanium nitride (wherein the titanium nitrideis Ti_(x)N_(y), y being equal to from about 0.01 to about 0.15) isdeposited as refractory metal 48, those portions of the Ti_(x)N_(y)layer in contact with the silicon source layer 42 will react during theanneal process to form a titanium silicide (e.g., TiSi_(x)N_(y)). Thusmetal silicide regions 52 are formed only in those areas where the localinterconnects are to be formed.

[0031] Referring to FIG. 1d, non-reacted refractory metal 48 is thenremoved from hard mask 46 using an etchant that is selective to theparticular metal silicide. For example, when use of an etchant selectiveto titanium silicide is appropriate, non-reacted refractory metal 48 ispreferably removed using a wet etch process, such as an etchant mixturecomprising NH₄OH/H₂O₂/H₂O (at a ratio of about 0.5:0.5:1). If refractorymetal 48 comprises cobalt or a cobalt compound, a preferred etchant maycomprise HNO₃/H₂O₂/H₂O (at a ratio of about 0.5:0.5:1). Such an etchantmixture is selective to cobalt silicide.

[0032] Referring to FIG. 1d, the remaining silicon source layer 42 neednot be removed as it is not a conductive material. Likewise, the hardmask 46 need not be removed. In some devices, it is preferable to havethe hard mask 46 remain, as the hard mask may act as a protective layerfor the active areas of the device.

[0033] As illustrated in FIG. 1e, a passivation layer or interleveldielectric (ILD) 56 is deposited over hard mask 46 and metal silicideregions 52. ILD 56 is typically a silica substantially comprisingmaterials selected from a group consisting of silicon dioxide,borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), doped orundoped oxides, and mixtures thereof. Once the ILD 56 is deposited, itis preferable to planarize the uppermost surface 68 of the localinterconnect structure 10 by a suitable process, such as chemicalmechanical polishing (CMP).

[0034] A recess 60 is then patterned on the ILD 56 and the ILD isremoved as illustrated by phantom lines in FIG. 1e. Recess 60 (i.e., anelectrical contact hole) is formed in the ILD 56 adjacent to the gatestack 25 and is generally aligned with the active area 14. As usedherein, “generally aligned with a selected active area” is intended tomean positioned substantially perpendicular to a location where theactive area 14 is situated within the substrate 18. Although only asingle recess 60 is illustrated in FIG. 1e, multiple recesses may beformed in the passivation layer to form electrical connection to aselected active area 14. The etchant used to remove selected portions ofILD 56 to form recess 60 may be isotropic or anisotropic, but ispreferably selective to the metal silicide 52. A typical etchantcomprises CHF₃, CF₄, Ar, or a mixture thereof.

[0035] An electrically conductive layer is then applied to fill recess60 and complete an electrical contact 64 to the corresponding activearea 14 through the corresponding metal silicide region 52 (FIG. 3).Electrical contact 64 typically comprises suitable electricallyconductive materials, such as aluminum, copper, tungsten, or othersuitable conductor materials.

[0036] As shown in FIG. 3, the local interconnect structure 10 madeaccording to the above-described method comprises a substrate 18 havingactive areas 14 and isolation region 20 formed therein. Topographicalsub-structures, such as gate stacks 25 for formation of MOSFETs, areincluded according to the specific needs of the ultimate device to bemade (e.g., a memory device). The local interconnect structure 10 of thepresent invention further includes metal silicide regions 52 formingelectrical connecting portions of the local interconnects.Non-conductive silicon source layer portions 42 are located immediatelyadjacent the metal silicide regions 52. Hard mask 46 covers the siliconsource layer portions 42 and ILD 56 covers the hard mask 46 and metalsilicide regions 52 with the exception of those metal silicide regionslocated directly above active areas 14 at the electrical contact 64.Electrical contact 64 extends from the uppermost surface 68 of the localinterconnect structure 10 to the metal silicide region 52 overlying theactive area 14.

[0037] At this point, local interconnect structure 10 (as shown in FIG.3) of the present invention is complete. Local interconnect structure 10of the present invention may now undergo conventional processingdepending upon specific needs, such as further processing to form amemory device.

[0038] Another method of manufacture of another embodiment of the localinterconnect structure 110 (as shown in FIG. 6) of the present inventionis described with reference to FIGS. 4a-4 f and FIG. 5.

[0039] Referring to FIG. 4a, as with the above-described embodiment, asemiconductor or wafer substrate 118 includes one or more active regions114 defined in the substrate. The substrate 118 may comprise silicon,gallium arsenide, glass, an insulating material such as sapphire, or anyother substrate material upon which an integrated circuit wafer may befabricated. Active regions 114 are typically formed by doping specificportions of the substrate 118, as described above. One or more fieldoxide or isolation regions 120 are formed in the substrate 118, also asdescribed above with reference to the first method.

[0040] Materials are deposited on the substrate 118 and selectivelyremoved to form a desired topographical structure, such as one or moretransistor gate stacks 125. Although two complete gate stacks 125 areillustrated in FIGS. 4a-4 f and FIG. 6, there may be any number of gatestacks 125 or any number of a variety of topographical structures formedupon the substrate 118. Gate stack 125 may comprise a gate oxide 122having a transistor gate 124, typically comprising a polysilicon layer.Overlying the transistor gate 124 is a conductive layer 128, e.g., arefractory metal silicide layer. The conductive layer 128 typicallycomprises a refractory metal silicide including but not limited totitanium, tungsten, tantalum, or molybdenum silicide, e.g., tungstensilicide (WSi_(x)).

[0041] Overlying the conductive layer 128 of the gate stack 125 is aninsulating-material cap 136. Insulating cap 136 typically comprises anoxide or nitride such as a tetraethoxysilane (TEOS) oxide layer. Eachgate stack 125 may include one or more spacers 132 formed immediatelyadjacent the stacks, as described above and as shown in FIG. 4a and FIG.6.

[0042] As shown with the gate stack 125 positioned on the right side ofthe structure shown in FIG. 4, a selected portion of the cap 136 may beremoved (e.g., by dry etch) to allow access to the transistor gate 124via the conductive layer 128. Alternatively, the cap 136 may beinitially deposited such that a portion of the conductive layer 128 isexposed to allow access to the transistor gate 124.

[0043] Continuing to refer to FIG. 4a, a uniform layer of a refractorymetal 148 (or other material capable of forming a silicide) is depositedover exposed portions of substrate 118, exposed portions of isolationregions 120, spacers 132, and caps 136. The refractory metal 148 may besputter deposited or may be deposited by any other suitable method. Therefractory metal 148 preferably comprises titanium, titanium nitride(Ti_(x)N_(y)), cobalt, or colbalt nitride. The refractory metal 148 ispreferably deposited at a thickness of from about 300 Å to about 500 Å.

[0044] Referring to FIG. 4b, a silicon source layer 142 is depositeduniformly over the refractory metal 148. Silicon source layer 142preferably comprises a silicon-rich silicon nitride film or a siliconoxynitride film (each compound having stoichiometries substantially asdescribed above in reference to the embodiment shown in FIGS. 1b-1 e).Silicon source layer 142 should have sufficient free siliconconcentration to form the necessary silicide (i.e., so that the silicideis sufficiently electrically conductive) but not so much free silicon asto cause stringer formation during the silicide process (such as occurswhen using polysilicon). Silicon-rich silicon nitride or siliconoxynitride may be deposited as described above in relation to the firstembodiment or by any other suitable deposition techniques as known topersons skilled in the art. The silicon source layer 142 preferably hasa thickness of from about 150 Å to about 400 Å and more preferably fromabout 150 Å to about 200 Å.

[0045] Silicon source layer 142 is patterned and selectively removed (asshown in FIG. 4c) to form partial source layer 146. That is, siliconsource layer 142 is patterned such that removal of portions of thesource layer forms partial source layer 146 (i.e., a hard mask), whichin turn defines the location(s) of the local interconnect. Referring toFIG. 4c, the portions of silicon source layer 142 that are then removedare those portions where local interconnection is not needed. Theselected portions of the silicon source layer 142 may he removed usingconventional etchants and etch methods, but are preferably removed usingan etchant that is selective to the refractory metal 148 (e.g., by dryetch).

[0046] The structure as shown in FIG. 4d is preferably annealed usingRTP in an N₂/NH₃ atmosphere at a temperature of from about 700° C. toabout 850° C., and more preferably at from about 700° C. to about 750°C. When the structure is annealed, refractory metal 148 in contact withthe partial source layer 146 form metal silicide regions 152 (as shownin FIG. 4e). The portions of the exposed refractory metal 148 (i.e.,those portions of refractory metal 148 wherein the silicon source layer142 overlying it was removed as described above) do not form a silicidecompound (i.e., remain as refractory metal and refractory metal nitride)except those portions in direct contact with the silicon substrate 118(i.e., at the active areas and local interconnect areas). For example,if Ti_(x)N_(y) is deposited as refractory metal 148, those portions ofthe titanium or titanium nitride layer in intimate and direct contactwith the partial source layer 146 will form a titanium suicide (e.g.,TiSi_(x)N_(y)) while those portions not directly in contact with partialsource layer 146 will remain as titanium or titanium nitride. Thus,metal silicide regions 152 are formed only in those areas in which thelocal interconnects are to be formed.

[0047] Referring to FIG. 4f, non-reacted refractory metal 148 is thenetched from the structure. The etchant used is selective to thematerials comprising exposed portions of the topographical structures(i.e., spacers 132, cap 136, isolation regions 120, and substrate 118).An oxide cap 170 is deposited uniformly over exposed portions of thetopographical structures (i.e., spacers 132, cap 136, isolation regions120, and substrate 118) and over metal silicide regions 152. Oxide cap170 may comprise a layer of oxide that provides a protective cap and ispreferably from about 300 Å to about 400 Å in thickness.

[0048] As illustrated in FIG. 4f, a passivation layer or interleveldielectric (ILD) 156 is deposited over oxide cap 170. ILD 156 typicallycomprises a silica substantially comprising materials selected from agroup consisting of silicon dioxide, borophosphosilicate glass (BPSG),phosphosilicate glass (PSG), doped or undoped oxides, and mixturesthereof, although other passivation materials may be used. Once the ILD156 is deposited, it is preferable to planarize the uppermost surface168 of the local interconnect structure 110 by a suitable process, suchas CMP. Prior to or instead of CMP, the structure may be annealed at atemperature of about 750° C. to about 900° C. to reflow ILD 156,resulting in a relatively smooth top layer.

[0049] A recess 160 is then patterned on ILD 156 and the selectedportion of ILD 156 is removed as illustrated by phantom lines in FIG.4f. Recess 160 (i.e., contact hole) is formed in ILD 156 adjacent togate stack 125 and is generally aligned with one or more selected activeareas 114. That is, although only a single recess 160 is illustrated inFIG. 4f, multiple recesses may be formed in ILD 156 to form electricalconnection to multiple selected active areas 114. The etchant used toremove selected portions of ILD 156 to form recess 160 may be isotropicor anisotropic but is preferably selective to the exposed portions ofthe structure described above. A typical etchant comprises CHF₃, CHF₄,or a mixture thereof.

[0050] An electrically conductive material is then deposited into recess160 to complete formation of an electrical contact 164 to the activearea 114 through the corresponding metal silicide region 152 (FIG. 6).Electrical contact 164 typically comprises an electrically conductivematerial, such as aluminum, copper, tungsten, or any other suitableconductor materials.

[0051] As shown in FIG. 6, the local interconnect structure 110 madeaccording to the above-described method comprises a substrate 118 havingactive areas 114 and isolation regions 120 formed therein. Topographicalsubstructures, such as gate stacks 125 of MOSFETs, are includedaccording to the specific needs for the ultimate device to be made(e.g., a memory device). The local interconnect structure 110 of thepresent invention further includes metal silicide regions 152 formingelectrical connecting portions of the local interconnects. Oxide cap 170covers metal silicide regions 152 and the exposed portions of spacers132, cap 136, isolation region 120, and substrate 118. Electricalcontact 164 extends from the uppermost portion 168 of the localinterconnect structure 110 to the metal silicide region 152 overlyingthe selected active area 114.

[0052] At this point, local interconnect structure 110 (as shown in FIG.6) of the present invention is complete. Local interconnect structure110 of the present invention may now undergo conventional processingdepending upon specific needs, such as further processing to form amemory device.

[0053] Whereas the invention has been described with reference tomultiple embodiments of the local interconnect structure andrepresentative methods, it will be understood that the invention is notlimited to those embodiments. On the contrary, the invention is intendedto encompass all modifications, alternatives, and equivalents as may beincluded within the spirit and scope of the invention as defined by theappended claims.

1. A method of forming a local interconnect structure for an integratedcircuit comprising: providing a substrate having a surface and includingat least one topographical structure thereon such that a region of thesurface of the substrate is exposed; forming at least one active area inthe substrate; forming a silicon source layer over the at least oneactive area and at least a portion of the at least one topographicalstructure; depositing a refractory metal directly on selected regions ofthe silicon source layer and over the at least one topographicalstructure; forming a silicide layer from the refractory metal andsilicon source layer, the suicide layer defining a portion of the localinterconnect structure; removing the refractory metal; forming aninterlevel dielectric over the silicide layer, the interlevel dielectrichaving a recess defined substantially over the at least one active area;and depositing an electrically conductive material in the recess.
 2. Themethod of claim 1, wherein the silicon source layer is selected from thegroup consisting essentially of silicon rich silicon nitride, siliconoxynitride, and mixtures thereof.
 3. The method of claim 1, wherein thesilicon source layer comprises Si_(x)N_(y)O_(z) wherein x is about 0.39to about 0.65, y is about 0.02 to about 0.56, and z is about 0.05 toabout 0.33.
 4. The method of claim 1, wherein the silicon source layerdoes not comprise polysilicon.
 5. The method of claim 1, wherein therefractory metal is selected from the group consisting essentially oftitanium, titanium nitride, cobalt, cobalt nitride, and mixturesthereof.
 6. The method of claim 5, wherein the refractory metal isTi_(x)N_(y), wherein y is from about 0.01 to about 0.15.
 7. The methodof claim 1, wherein the refractory metal is removed using an etchantthat is selective to the refractory metal silicide.
 8. A method offorming a local interconnect structure for an integrated circuitcomprising: providing a substrate having an exposed surface portion andan exposed active area; depositing a silicon source layer over theactive area and exposed surface portion; forming a thin film over thesilicon source layer; patterning and removing selected regions of thethin layer to expose regions of the silicon source layer to define alocal interconnect pattern on the silicon source layer; depositing asilicide forming material on exposed regions of the silicon sourcelayer; reacting the silicide forming material with the exposed regionsof the silicon source layer to form a silicide layer as part of thelocal interconnect structure; removing the silicide forming material;forming an interlevel dielectric over the silicide layer, the interleveldielectric having a recess defined therein and substantially alignedwith and extending to the active area; and depositing an electricallyconductive material in the recess.
 9. The method of claim 8, wherein thesilicon source layer is selected from the group consisting essentiallyof silicon rich silicon nitride, silicon oxynitride, and mixturesthereof.
 10. The method of claim 8, wherein the silicon source layercomprises Si_(x)N_(y)O_(z) wherein x is about 0.39 to about 0.65, y isabout 0.02 to about 0.56, and z is about 0.05 to about 0.33.
 11. Themethod of claim 8, wherein the thin film comprises a hard mask.
 12. Amethod of forming a local interconnect structure for an integratedcircuit comprising: providing a substrate having a principal surfaceincluding at least one topographical structure thereon such that asubstrate region of the principal surface is exposed; forming at leastone active area in the substrate adjacent the at least one topographicalstructure; forming a silicon source layer over the substrate region ofthe principal surface; forming a hard mask on selected silicon sourcelayer regions such that the silicon source layer regions that form partof the local interconnect structure remain exposed; forming a refractorymetal over the hard mask and on the silicon source layer regions;annealing to form a portion of the local interconnect structure;removing refractory metal from the hard mask; forming an interleveldielectric over the portion of the local interconnect structure and thehard mask, the interlevel dielectric having a recess defined therein andsubstantially aligned with the active area or the topographicalstructure; and depositing an electrically conductive material in therecess.
 13. The method of claim 12, wherein the silicon sources layerdoes not comprise polysilicon.
 14. The method of claim 12, wherein theresulting local interconnect structure is substantially free ofstringers.
 15. A method of manufacturing a semiconductor devicecomprising: providing a substrate having a principal surface includingat least one gate stack formed thereon such that a region of theprincipal surface of the substrate is exposed; forming an active area inthe substrate immediately adjacent the gate stack; forming a siliconsource layer over at least a portion of the active area and over atleast a portion of the gate stack; depositing a refractory metal onselected regions of the silicon source layer; creating a silicide layerfrom the refractory metal and silicon source layer, the silicide layerforming a portion of a local interconnect structure; forming apassivation layer on the silicide layer and silicon source layer, thepassivation layer having a recess formed therein, the recess beingsubstantially aligned with a portion of the silicide layer; anddepositing an electrically conductive material in the recess.
 16. Themethod of claim 15, wherein the silicide layer is formed by an annealingprocess.
 17. A method of manufacturing an integrated circuit comprising:forming an active area in a substrate; forming a topographical device onthe substrate; forming a silicon source layer over a surface of thesubstrate and over at least a portion of the topographical structure,the silicon source layer comprising a material selected from the groupconsisting essentially of silicon rich silicon nitride, siliconoxynitride, and mixtures thereof; forming a hard mask on the siliconsource layer to define a local interconnect pattern thereon; depositinga uniform layer of a refractory metal on the silicon source layer and onthe hard mask; forming a refractory metal silicide layer; removingrefractory metal overlying the hard mask; forming an interleveldielectric over the silicide layer and hard mask, the interleveldielectric having a recess defined substantially over the active area ora portion of the topographical structure; and depositing an electricallyconductive material in the recess.
 18. The method of claim 17, whereinthe refractory metal is selected from the group consisting essentiallyof titanium, titanium nitride, cobalt, cobalt nitride, and mixturesthereof.
 19. The method of claim 17, wherein the refractory metal isTi_(x)N_(y), wherein y is equal to about 0.01 to about 0.15.
 20. Themethod of claim 17, wherein the silicon source layer is selected fromthe group consisting essentially of silicon rich silicon nitride,silicon oxynitride, and mixtures thereof.
 21. A method of manufacturinga semiconductor device comprising: providing a substrate having at leastone gate stack formed thereon such that a region of the substrate isexposed; forming at least one active area in the substrate adjacent theat least one gate stack; removing a portion of the at least one gatestack to provide electrical access to a gate in the at least one gatestack; forming a silicon source layer over the at least one active areaand over at least a portion of the at least one gate stack; depositing arefractory metal on selected regions of the silicon source layer;creating a silicide layer from the refractory metal and silicon sourcelayer, the silicide layer forming a portion of a local interconnectstructure; forming a passivation layer on the silicide layer, thepassivation layer having recesses formed therein, the recesses beingsubstantially aligned with the at least one active area or the at leastone gate stack; and depositing an electrically conductive material inthe recesses.
 22. The method of claim 21, wherein a hard mask isdeposited on selected portions of the silicon source layer prior todeposition of the refractory metal.
 23. The method of claim 21, whereinthe silicon source layer is selected from the group consistingessentially of silicon rich silicon nitride, silicon oxynitride, andmixtures thereof.
 24. A method of forming a local interconnect structurefor an integrated circuit comprising: providing a substrate on which asurface of the substrate and an active area are exposed; depositing arefractory metal over at least a portion of the active area and theexposed surface of the substrate; depositing a silicon source layer overthe refractory metal; patterning and removing selected regions of thesilicon source layer to expose regions of the refractory metal defininga local interconnect pattern; reacting regions of the silicon sourcelayer with the refractory metal creating a local interconnect structure;removing un-reacted refractory metal; forming an interlevel dielectrichaving a recess defined therein and substantially aligned with theactive area; and depositing an electrically conductive material in therecess.
 25. The method of claim 24, wherein the silicon source layer isselected from the group consisting essentially of silicon rich siliconnitride, silicon oxynitride, and mixtures thereof.
 26. The method ofclaim 24, wherein the silicon source layer comprises Si_(x)N_(y)O_(z)wherein x is about 0.39 to about 0.65, y is about 0.02 to about 0.56,and z is about 0.05 to about 0.33.
 27. The method of claim 24, whereinthe silicon source layer does not comprise polysilicon.
 28. The methodof claim 24, wherein the refractory metal is selected from the groupconsisting essentially of titanium, titanium nitride, cobalt, cobaltnitride, and mixtures thereof.
 29. The method of claim 24, wherein therefractory metal is removed using an etchant that is selective to arefractory metal silicide.
 30. A method of forming a local interconnectstructure for an integrated circuit comprising: providing a substratehaving a surface and including at least one topographical structurethereon such that a region of the surface of the substrate is exposed;forming an active area in the substrate; depositing a silicide formingmaterial over the active area and at least a portion of thetopographical structure; depositing a silicon source layer on selectedregions of the silicide forming material; making a silicide layer fromthe silicide forming material and silicon source layer, the silicidelayer creating a portion of the local interconnect structure; removingun-reacted silicide forming material; forming an oxide cap over thesilicide layer, exposed portions of the topographical structure, and thesubstrate; forming a passivation layer over the oxide cap; defining atleast one recess extending through the passivation layer and the oxidecap, the recess substantially aligned over the active area or a portionof the topographical structure; and depositing an electricallyconductive material in the recess.
 31. The method of claim 30, whereinthe silicon source layer is selected from the group consistingessentially of silicon rich silicon nitride, silicon oxynitride, andmixtures thereof.
 32. The method of claim 30, wherein the silicon sourcelayer comprises Si_(x)N_(y)O_(z) wherein x is about 0.39 to about 0.65,y is about 0.02 to about 0.56, and z is about 0.05 to about 0.33. 33.The method of claim 30, wherein the silicon source layer does notcomprise polysilicon.
 34. A method of manufacturing an integratedcircuit device comprising: providing a substrate having a surfaceincluding at least one topographical structure thereon such that aregion of the surface of the substrate is exposed; forming at least oneactive area in the substrate adjacent the at least one topographicalstructure; forming a refractory metal over the exposed region of thesubstrate, at least a portion of the at least one active area, and atleast a portion of the at least one topographical structure; forming asilicon source layer over the refractory metal; patterning and removingselected portions of the silicon source layer such that selected regionsof the refractory metal structure are exposed; annealing to form arefractory metal silicide; removing un-reacted refractory metal afterthe refractory metal silicide is formed; forming an interleveldielectric having a recess defined therein and substantially alignedwith at least a portion of the at least one active area or at least aportion of the at least one topographical structure; and depositing anelectrically conductive material in the recess.
 35. The method of claim34, wherein the silicon source layer comprises Si_(x)N_(y)O_(z) whereinx is about 0.39 to about 0.65, y is about 0.02 to about 0.56, and z isabout 0.05 to about 0.33.
 36. The method of claim 34, wherein thesilicon source layer is selected from the group consisting essentiallyof silicon rich silicon nitride, silicon oxynitride, and mixturesthereof.
 37. A method of manufacturing a semiconductor devicecomprising: providing a substrate having at least one gate stackthereon; forming at least one active area in the substrate immediatelyadjacent the at least one gate stack; forming a refractory metal over aportion of the at least one active area and over at least a portion ofthe at least one gate stack; depositing a silicon source layer on therefractory metal; removing selected regions of the silicon source layerto define a local interconnect structure over a portion of the at leastone active area or the at least one gate stack; reacting refractorymetal covered by the silicon source layer with the silicon source layerto form a silicide layer; forming an oxide cap over the silicide layer,exposed portions of the at least one gate stack and the substrate;forming a passivation layer over the oxide cap; defining at least onerecess extending through the passivation layer and the oxide cap, therecess substantially aligned over a portion of the at least one activearea or the at least one gate stack; and depositing an electricallyconductive material in the recess.
 38. A method of manufacturing anintegrated circuit comprising: forming an active area in a substrate;forming a topographical device on the substrate; depositing a layer of arefractory metal over a surface of the substrate and over thetopographical structure forming a silicon source layer over therefractory metal, the silicon source layer comprising a materialselected from the group consisting essentially of silicon rich siliconnitride, silicon oxynitride, and mixtures thereof; removing selectedregions of the silicon source layer to define a local interconnectpattern on the refractory metal; forming a refractory metal silicidelayer from the refractory metal and the silicon source layer to form aportion of a local interconnect structure; removing refractory metalafter the refractory metal silicide is formed; forming an interleveldielectric over the silicide layer, the interlevel dielectric havingrecesses defined substantially over a portion of the active area and aportion of the topographical structure; and depositing an electricallyconductive material in the recesses.
 39. An integrated circuit formed ona substrate, the integrated circuit having at least one localinterconnect structure comprising: at least one gate stack on thesubstrate; at least one active area adjacent the at least one gatestack; a silicon source layer overlying a portion of the substrate and aportion of the at least one gate stack; a silicide layer overlying theat least one active area and extending over a portion of the at leastone gate stack; an oxide layer overlying the silicon source layer butnot the silicide layer; a passivation layer overlying the oxide layerand the silicide layer, the passivation layer having at least one recessdefined therein, the at least one recess terminating substantially atthe at least one active area or the at least one gate stack; and anelectrically conductive material disposed in and substantially fillingthe recess, the electrically conductive material forming an electricalcontact with the silicide layer and the at least one active area or theat least one gate stack.
 40. The method of claim 39, wherein the siliconsource layer is selected from the group consisting essentially ofsilicon rich silicon nitride, silicon oxynitride, and mixtures thereof.41. The method of claim 39, wherein the silicon source layer comprisesSi_(x)N_(y)O_(z) wherein x is about 0.39 to about 0.65, y is about 0.02to about 0.56, and z is about 0.05 to about 0.33.
 42. The method ofclaim 39, wherein the silicon source layer does not comprisepolysilicon.
 43. The method of claim 39, wherein the refractory metal isselected from the group consisting essentially of titanium, titaniumnitride, cobalt, cobalt nitride, and mixtures thereof.
 44. The method ofclaim 39, wherein the refractory metal is Ti_(x)N_(y), wherein y is fromabout 0.01 to about 0.15.
 45. A local interconnect structure comprising:a semiconductor substrate having at least one topographical structurethereon; at least one active area adjacent the at least onetopographical structure; a silicon source layer overlying a portion ofthe semiconductor substrate and a portion of the at least onetopographical structure; a metal silicide layer overlying the at leastone active area and extending over a portion of the at least onetopographical structure; a hard mask layer overlying the silicon sourcelayer but not overlying the metal silicide layer; an interleveldielectric overlying the hard mask layer and the metal silicide layer,the interlevel dielectric having a recess defined therein extendingsubstantially to the at least one active area; and an electricallyconductive material disposed in and substantially filling the recess,the electrically conductive material forming an electrical contact withthe metal silicide and the at least one active area.